1. Field of the Invention
The present invention relates to semiconductor memory devices and particularly to an improvement of a test mode decision circuit in a dynamic random access memory (DRAM).
2. Description of the Background Art
DRAMs in general have more than one test mode. A DRAM enters a test mode when a test mode decision circuit provided in the DRAM detects the test mode. To prevent the DRAM from erroneously entering the test mode when an ordinary user is normally using the DRAM, the test mode decision circuit is configured to detect a super VIH level higher than a logical high level that is applied to an address pin in a WCBR (WE (a write enable signal), CAS (a column address strobe signal) and BEFORE RAS (a row address strobe signal)) cycle.
However, conventional DRAMs cannot enter more than one test mode simultaneously. In contrast, Japanese Patent Laying-Open No. 5-242698 discloses a DRAM capable of entering more than one test mode simultaneously. Once it has entered a test mode, however, the DRAM cannot enter another test mode. As such, the DRAM must first exit the test mode and thereafter enter two test modes simultaneously.
Furthermore, in a conventional DRAM a refresh operation is performed whenever the DRAM enters a test mode. As such, in the DRAM the refresh operation is performed when the DRAM already in a test mode also enters another test mode, so that the first test cannot be run accurately.
Furthermore, a DRAM can erroneously enter a test mode when the write enable signal, the column address strobe signal and the row address strobe signal are erroneously input in the WCBR cycle and the address pin also receives a high-voltage noise.
Japanese Patent Laying-Open No. 10-247399 discloses a DRAM which allows three different password signals to be input in three WCBR cycles and stored in a register and in the fourth WCBR cycle responds to an input address by entering a predetermined test mode. This DRAM, however, cannot enter more than one test mode simultaneously.